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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b copyright ? 2014 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances features ? 100 percent bus utilization ? no wait cycles between read and write ? internal self-timed write cycle ? individual byte write control ? single r/w (read/write) control pin ? clock controlled, registered address, data and control ? interleaved or linear burst sequence control us - ing mode input ? three chip enables for simple depth expansion and address pipelining ? power down mode ? common data inputs and data outputs ? cke pin to enable clock and suspend operation ? jedec 100-pin tqfp, 165-ball pbga and 119- ball pbga packages ? power supply: nlp: v dd 3.3v ( 5%), v ddq 3.3v/2.5v ( 5%) nvp: v dd 2.5v ( 5%), v ddq 2.5v ( 5%) nvvp: v dd 1.8v ( 5%), v ddq 1.8v ( 5%) ? jtag boundary scan for pbga packages ? industrial temperature available ? lead-free available description the 72 meg product family features high-speed, low-power synchronous static rams designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. they are organized as 2,096,952 words by 36 bits and 4,193,904 words by 18 bits, fabricated with issi 's advanced cmos technology. incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cke is high. in this state the internal device will hold their previous values. all read, write and deselect cycles are initiated by the adv input. when the adv is high the internal burst counter is incremented. new external addresses can be loaded when adv is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when we is low. separate byte enables allow individual bytes to be written. a burst mode pin (mode) defnes the order of the burst sequence. when tied high, the interleaved burst sequence is selected. when tied low, the linear burst sequence is selected. 2m x 36 and 4m x 18 72mb, pipeline 'no wait' state bus sram august 2014 symbol parameter 250 200 166 units t kq clock access time 2.8 3.1 3.8 ns t kc cycle time 4 5 6 ns frequency 250 200 166 mhz fast access time
2 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b block diagram a ddr e s s r e g i s t e r s c o n t r o l r e g i s t e r c l k / c k e / c e c e 2 / c e 2 a d v / w e /bw x ( x = a , b ,c, d o r a , b ) c o n t r o l log i c k / o e zz k a ddr e ss r e g i ste r s a ddr e ss r e g i s t e r s b u r st l o g i c k m o d e a d v a 0 - a 1 a ' 0 - a ' 1 a 2 - 20( a 2 - a 21) a 0 - 20 ( a 0 - 21) a 0 - 20 ( a 0 - 21) 2 m x 36; 4mx 1 8 m e m o r y a r r a y d a t a - i n r egi s t e r d a t a - i n r egi s t e r k k o u t p u t r egi s t e r k o u t p u t b u f f ers a 0 - 20( a 0 - 21) 3 6 ( 1 8 ) d q x / d q p x
integrated silicon solution, inc. www.issi.com 3 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b bottom view bottom view 165-pin bga 165-ball, 13x15 mm bga 165-ball, 15x17 mm bga 1 mm ball pitch, 11 x 15 ball array 119- pin bga 119-ball, 14x22 mm bga 1.27 mm ball pitch, 7 x 17 ball array
4 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b note: a0 and a1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. pin descriptions symbol pin name a synchronous address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke synchronous clock enable ce, ce2, ce2 synchronous chip enable bwa-bwd synchronous byte write inputs oe asynchronous output enable zz asynchronous power sleep mode mode burst sequence selection tck, tdi jtag pins tdo, tms v dd power supply nc no connect dqa-dqd synchronous data inputs/outputs dqpa-dqpd synchronous parity data inputs/outputs v ddq i/o power supply v ss g round pin c onfiguration 2m x 36, 165- ball pbga (t op view) 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwc bwb ce2 cke adv a a nc b nc a ce2 bwd bwa clk we oe a a nc c dqpc nc vddq vss vss vss vss vss vddq nc dqpb d dqc dqc vddq vdd vss vss vss vdd vddq dqb dqb e dqc dqc vddq vdd vss vss vss vdd vddq dqb dqb f dqc dqc vddq vdd vss vss vss vdd vddq dqb dqb g dqc dqc vddq vdd vss vss vss vdd vddq dqb dqb h nc nc nc vdd vss vss vss vdd nc nc zz j dqd dqd vddq vdd vss vss vss vdd vddq dqa dqa k dqd dqd vddq vdd vss vss vss vdd vddq dqa dqa l dqd dqd vddq vdd vss vss vss vdd vddq dqa dqa m dqd dqd vddq vdd vss vss vss vdd vddq dqa dqa n dqpd nc vddq vss nc nc nc vss vddq nc dqpa p nc a a a tdi a1* tdo a a a nc r mode a a a tms a0* tck a a a a
integrated silicon solution, inc. www.issi.com 5 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b 119-pin pbga package configuration 2m x 36 (top view) note: a0 and a1 are the two least signifcant bits(lsb) of the address feld and set the internal burst counter if burst is desired. pin descriptions symbol pin name a synchronous address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke synchronous clock enable ce synchronous chip select ce2 synchronous chip select ce2 synchronous chip select bwa-bwd synchronous byte write inputs oe asynchronous output enable zz asynchronous power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi v dd power supply v ss ground nc no connect dqa-dqd synchronous data inputs/outputs dqpa-dqpd synchronous parity data inputs/outputs v ddq i/o power supply 1 2 3 4 5 6 7 a vddq a a a a a vddq b nc ce2 a adv a ce2 nc c nc a a vdd a a nc d dqc dqpc vss nc vss dqpb dqb e dqc dqc vss ce vss dqb dqb f vddq dqc vss oe vss dqb vddq g dqc dqc bwc a bwb dqb dqb h dqc dqc vss we vss dqb dqb j vddq vdd nc vdd nc vdd vddq k dqd dqd vss clk vss dqa dqa l dqd dqd bwd nc bwa dqa dqa m vddq dqd vss cke vss dqa vddq n dqd dqd vss a1* vss dqa dqa p dqd dqpd vss a0* vss dqpa dqa r nc a mode vdd nc a nc t nc a a a a a zz u vddq tms tdi tck tdo nc vddq
6 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b 165-pin pbga package configuration 4m x 18 (top view) pin descriptions symbol pin name a synchronous address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke synchronous clock enable ce, ce2, ce2 synchronous chip enable bwa-bwb synchronous byte write inputs oe asynchronous output enable zz asynchronous power sleep mode note: a0 and a1 are the two least signifcant bits (lsb) of the address feld and set the internal burst counter if burst is desired. mode burst sequence selection tck, tdi jtag pins tdo, tms v dd power supply nc no connect dqa-dqb synchronous data inputs/outputs dqpa-dqpb synchronous parity data inputs/outputs v ddq i/o power supply v ss g round 1 2 3 4 5 6 7 8 9 10 11 a nc a ce bwb nc ce2 cke adv a a a b nc a ce2 nc bwa clk we oe a a nc c nc nc vddq vss vss vss vss vss vddq nc dqpa d nc dqb vddq vdd vss vss vss vdd vddq nc dqa e nc dqb vddq vdd vss vss vss vdd vddq nc dqa f nc dqb vddq vdd vss vss vss vdd vddq nc dqa g nc dqb vddq vdd vss vss vss vdd vddq nc dqa h nc nc nc vdd vss vss vss vdd nc nc zz j dqb nc vddq vdd vss vss vss vdd vddq dqa nc k dqb nc vddq vdd vss vss vss vdd vddq dqa nc l dqb nc vddq vdd vss vss vss vdd vddq dqa nc m dqb nc vddq vdd vss vss vss vdd vddq dqa nc n dqpb nc vddq vss nc nc nc vss vddq nc nc p nc a a a tdi a1* tdo a a a nc r mode a a a tms a0* tck a a a a
integrated silicon solution, inc. www.issi.com 7 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b 119-pin pbga package configuration 4m x 18 (top view) pin descriptions symbol pin name a synchronous address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke synchronous clock enable ce synchronous chip select ce2 synchronous chip select ce2 synchronous chip select bwa-bwb synchronous byte write inputs oe asynchronous output enable zz asynchronous power sleep mode mode burst sequence selection tck, tdo jtag pins tms, tdi v dd power supply v ss ground nc no connect dqa-dqb synchronous data inputs/outputs dqpa-dqpb synchronous parity data inputs/outputs v ddq i/o power supply note: a0 and a1 are the two least signifcant bits(lsb) of the address feld and set the internal burst counter if burst is desired. 1 2 3 4 5 6 7 a vddq a a a a a vddq b nc ce2 a adv a ce2 nc c nc a a vdd a a nc d dqb nc vss nc vss dqpa nc e nc dqb vss ce vss nc dqa f vddq nc vss oe vss dqa vddq g nc dqb bwb a nc nc dqa h dqb nc vss we vss dqa nc j vddq vdd nc vdd nc vdd vddq k nc dqb vss clk vss nc dqa l dqb nc nc nc bwa dqa nc m vddq dqb vss cke vss nc vddq n dqb nc vss a1* vss dqa nc p nc dqpb vss a0* vss nc dqa r nc a mode vdd nc a nc t a a a a a a zz u vddq tms tdi tck tdo nc vddq
8 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b pin configuration 100-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dqpb dqb dqb v ddq vss dqb dqb dqb dqb vss v ddq dqb dqb vss nc v dd zz dqa dqa v ddq vss dqa dqa dqa dqa vss v ddq dqa dqa dqp a dqpc dqc dqc v ddq vss dqc dqc dqc dqc vss v ddq dqc dqc nc v dd nc vss dqd dqd v ddq vss dqd dqd dqd dqd vss v ddq dqd dqd dqpd a a ce ce2 bwd bwc bwb bwa ce2 v dd vss clk we cke oe ad v a a a a mode a a a a a1 a0 nc nc vss v dd a a a a a a a a a 2m x 36 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adv synchronous burst address advance - synchronous byte write enable synchronous write enable synchronous clock enable vss ground for core nc not connected , ce2, ce2 synchronous chip enable oe asynchronous output enable dqa-dqd synchronous data inputs/outputs dqpa-dqpd synchronous parity data inputs/outputs mode burst sequence selection v dd power supply v ss ground for output buffer v ddq i/o power supply zz asynchronous snooze enable
integrated silicon solution, inc. www.issi.com 9 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b pin configuration 100-pin tqfp 4m x 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a nc nc v ddq vss nc dqp a dqa dqa vss v ddq dqa dqa vss nc v dd zz dqa dqa v ddq vss dqa dqa nc nc vss v ddq nc nc nc nc nc nc v ddq vss nc nc dqb dqb vss v ddq dqb dqb nc v dd nc vss dqb dqb v ddq vss dqb dqb dqpb nc vss v ddq nc nc nc a a ce ce2 nc nc bwb bwa ce2 v dd vss clk we cke oe ad v a a a a mode a a a a a1 a0 nc nc vss v dd a a a a a a a a a pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adv synchronous burst address advance - synchronous byte write enable synchronous write enable synchronous clock enable vss ground for core nc not connected , ce2, ce2 synchronous chip enable oe asynchronous output enable dqa-dqb synchronous data inputs/outputs dqpa-dqpb synchronous parity data inputs/outputs mode burst sequence selection v dd power supply v ss ground for output buffer v ddq i/o power supply zz asynchronous snooze enable
10 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b synchronous truth table (1) address operation used ce ce2 ce2 adv we bwx oe cke clk not selected n/a h x x l x x x l not selected n/a x l x l x x x l not selected n/a x x h l x x x l not selected continue n/a x x x h x x x l begin burst read external address l h l l h x l l continue burst read next address x x x h x x l l nop/dummy read external address l h l l h x h l dummy read next address x x x h x x h l begin burst write external address l h l l l l x l continue burst write next address x x x h x l x l nop/write abort n/a l h l l l h x l write abort next address x x x h x h x l ignore clock current address x x x x x x x h notes: 1. "x" means don't care. 2. the rising edge of clock is symbolized by 3. a continue deselect cycle can only be entered if a deselect cycle is executed frst. 4. we = l means write operation in write truth table. we = h means read operation in write truth table. 5. operation fnally depends on status of asynchronous pins (zz and oe). burst read deselect burs t write begin read begin write read write read write burs t burst burs t ds ds ds read ds ds read write write burst burs t write read state diagram
integrated silicon solution, inc. www.issi.com 11 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b asynchronous truth table (1) operation zz oe i/o status sleep mode h x high-z read l l dq l h high-z write l x din, high-z deselected l x high-z notes: 1. x means "don't care". 2. for write cycles following read cycles, the output buffers must be disabled with oe, otherwise data bus contention will occur. 3. sleep mode means power sleep mode where stand-by current does not depend on cycle time. 4. deselected means power sleep mode where stand-by current depends on cycle time. write truth table (x18) operation we bwa bwb read h x x write byte a l l h write byte b l h l write all bytes l l l write abort/nop l h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk.
12 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b interleaved burst address table (mode = v dd or nc) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 write truth table (x36) operation we bwa bwb bwc bwd read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h notes : 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk. power u p seq uence v ddq v dd 1 i/o pins 2 notes : 1. v dd can be applied at the same time as v ddq 2. a pplying i/o inputs is recommended after v ddq is ready. the inputs of the i/o pins can be applied at the same time as v ddq provided v ih (level of i/o pins) is lower than v ddq . power-up i n itialization timing vdd device initialization power > 1ms device ready fo r normal operatio n vdd vddq
integrated silicon solution, inc. www.issi.com 13 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b linear burst address table (mode = v ss ) absolute maximum ratings (1) symbol parameter nlp value nvp/nvvp value unit t stg storage temperature C65 to +150 C65 to +150 c p d power dissipation 1.6 1.6 w i out output current (per i/o) 100 100 ma v in , v out voltage relative to v ss for i/o pins C0.5 to v ddq + 0.3 C0.5 to v ddq + 0.3 v v in voltage relative to v ss for C0.3 to v dd +0.5 C0.3 to v dd +0.3 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may af fect reliability. 2. this device contains circuitry to protect the inputs against damage due to high static voltages or electric felds; however, precau - tions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1 operating range (is61nlpx) range ambient temperature v dd v ddq commercial 0c to +70c 3.3v 5% 3.3v / 2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v / 2.5v 5% operating range (is61nvpx) range ambient temperature v dd v ddq commercial 0c to +70c 2.5v 5% 2.5v 5% industrial -40c to +85c 2.5v 5% 2.5v 5% operating range (is61nvvpx) range ambient temperature v dd v ddq commercial 0c to +70c 1.8v 5% 1.8v 5% industrial -40c to +85c 1.8v 5% 1.8v 5%
14 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b power supply characteristics (1) (over operating range) -250 -200 -166 max max max symbol parameter test conditions temp. range x18 x36 x18 x36 x18 x36 uni t i cc ac operating device selected, com. 450 450 400 400 350 350 ma supply current oe = v ih , zz v il , i nd. 500 500 450 450 400 400 all inputs 0.2v or v dd C 0.2v, cycle time t kc min. i sb standby current device deselected, com. 200 200 200 200 200 200 ma ttl input v dd = max., ind. 220 220 220 220 220 220 all inputs v il or v ih , zz v il , f = max. i sbi standby current device deselected, com. 180 180 180 180 180 180 ma c mos input v dd = max., ind. 200 200 200 200 200 200 v in d v ss + 0.2v or v dd C 0.2v f = 0 dc electrical characteristics (over operating range) 1, 2, 3 3.3v 2.5v 1.8v symbol parameter test conditions min. max. min. max. min. max. unit v oh output high voltage i oh = C4.0 ma (3.3v) 2.4 2.0 v ddq - 0.4 v i oh = C1.0 ma (2.5v, 1.8v) v ol output low voltage i ol = 8.0 ma (3.3v) 0.4 0.4 0.4 v i ol = 1.0 ma (2.5v, 1.8v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 0.6 v dd v dd + 0.3 v v il input low voltage C0.3 0.8 C0.3 0.7 C0.3 0.3 v dd v i li input leakage current v ss d v in v dd (1,4) C5 5 C5 5 C5 5 a input current of mode v ss d v in v dd (5) C30 5 C30 5 C30 5 input current of zz v ss d v in v dd (6) C5 30 C5 30 C5 30 i lo output leakage current v ss d v out v ddq , oe = v ih C5 5 C5 5 C5 5 a notes: 1. all voltages referenced to ground. 2. overshoot: 3.3v and 2.5v: v ih (ac) v dd + 1.5v (pulse width less than t kc /2) 1.8v: v ih (ac) v dd + 0.5v (pulse width less than t kc /2) 3. undershoot: 3.3v and 2.5v: v il (ac) -1.5v (pulse width less than t kc /2) 1.8v: v il (ac) -0.5v (pulse width less than t kc /2) 4. except mode and zz 5. mode is connected to pull-up resister internally. 6. zz is connected to pull-down resister internally.
integrated silicon solution, inc. www.issi.com 15 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 317 5 pf including jig and scope 351 output +3.3v figure 1 figure 2 capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 3.3v i/o output load equivalent 1.5v output zo= 50? 50?
16 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 1.25v 50 output 1,667 5 pf including jig and scope 1,538 output +2.5v figure 3 figure 4 2.5v i/o output load equivalent 1.8v i/o ac test conditions parameter unit input pulse level 0v to 1.8v input rise and fall times 1.5 ns input and output timing 0.9v and reference level output load see figures 5 and 6 z o = 50 0.9v 50 output 1k 5 pf including jig and scope 1k output +1.8v figure 5 figure 6 1.8v i/o output load equivalent
integrated silicon solution, inc. www.issi.com 17 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b read/write cycle switching characteristics (1) (over operating range) -250 -200 -166 symbol parameter min. max. min. max. min. max. unit fmax clock frequency 250 200 166 mhz t kc cycle time 4.0 5 6 ns t kh clock high time 1.7 2 2.4 ns t kl clock low time 1.7 1.7 2.3 ns t kq clock access time 2.8 3.1 3.8 ns t kqx (2) clock high to output invalid 0.8 1.5 1.5 ns t kqlz (2,3) clock high to output low-z 0.8 1 1.5 ns t kqhz (2,3) clock high to output high-z 2.8 3.1 3.8 ns t oeq output enable to output valid 2.8 3.1 3.8 ns t oelz (2,3) output enable to output low-z 0 0 0 ns t oehz (2,3) output disable to output high-z 2.8 3.1 3.8 ns t as address setup time 1.4 1.4 1.5 ns t ws read/write setup time 1.4 1.4 1.5 ns t ces chip enable setup time 1.4 1.4 1.5 ns t se clock enable setup time 1.4 1.4 1.5 ns t advs address advance setup time 1.4 1.4 1.5 ns t ds data setup time 1.4 1.4 1.5 ns t ah address hold time 0.4 0.4 0.5 ns t he clock enable hold time 0.4 0.4 0.5 ns t wh write hold time 0.4 0.4 0.5 ns t ceh chip enable hold time 0.4 0.4 0.5 ns t advh address advance hold time 0.4 0.4 0.5 ns t dh data hold time 0.4 0.4 0.5 ns t power (4) v dd (typical) to first access 1 1 1 ms notes: 1. confguration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2. 4. t power is the time that the power needs to be supplied above v dd (min) initially before read or write operation can be initiated.
18 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b sleep mode timing don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (e xcept zz) outputs (q) i sb2 zz setup cycle zz reco ve ry cycle nor mal operation cycle t pds t pus t zzi high-z snooze mode electrical chara cteristics symbol parameter conditions temperature min. max. unit r ange i sb 2 current during snooze mode zz v dd - 0.2v com. 80 ma ind. 90 auto. 100 t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to snooze current 2 cycle t rzzi zz inactive to exit snooze current 0 ns
integrated silicon solution, inc. www.issi.com 19 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b read cycle timing t ds clk ad v address write cke ce oe data out a1 a2 a3 t kh t kl t kc q3-3 q3-4 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 don't care undefined no tes: write = l means we = l and bwx = l we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l t oehz t se t he t as t ah t ws t wh t ces t ceh t advs t advh t kqhz t kq t oeq t oehz q1-1
20 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b write cycle timing t ds t dh clk ad v address write cke ce oe data in data out a1 a2 a3 t kh t kl t kc t se t he d3-3 d3-4 d3-2 d3-1 d2-4 d2-3 d2-2 d2-1 d1-1 don't care undefined no tes: write = l means we = l and bwx = l we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l t oehz q0-3 q0-4
integrated silicon solution, inc. www.issi.com 21 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b single read/write cycle timing clk c ke address w rite c e ad v o e data out data in d5 t se t he t kh t kl t kc don't care undefined no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l d2 t oelz t oeq a1 a2 a3 a4 a5 a6 a7 a8 a9 q1 q3 q4 q6 q7 t ds t dh
22 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b cke operation timing a1 a2 a3 a4 a5 a6 q1 q3 q4 clk cke address write ce ad v oe data out data in d2 t se t he t kh t kl t kc t kqlz t kqhz t kq t dh t ds don't care undefined no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l
integrated silicon solution, inc. www.issi.com 23 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b ce operation timing don't care undefined clk cke address write ce ad v oe data out data in t se t he t kh t kl t kc no tes: write = l means we = l and bwx = l ce = l means ce1 = l, ce2 = h and ce2 = l ce = h means ce1 = h, or ce1 = l and ce2 = h, or ce1 = l and ce2 = l d5 d3 t dh t ds t oelz t oeq q1 q2 q4 t kqhz t kqlz t kq a1 a2 a3 a4 a5
24 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b ieee 1149.1 s erial b oundary scan (jtag) the serial boundary scan test access port (tap) is only available in the pbga package. (not available in tqfp package.) this port operates in accordance with ieee standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. these functions from the ieee specifcation are excluded because they place added delay in the critical speed path of the sram. the tap controller operates in a manner that does not confict with the performance of other devices using 1149.1 fully compliant tap. disabling the jtag f eature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be disconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left disconnected. on power-up, the device will start in a reset state which will not interfere with the device operation. test access port (tap) - test clock the test clock is only used with the tap controller. all inputs are captured on the rising edge of tck and outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. this pin may be left disconnected if the tap is not used. the pin is internally pulled up, resulting in a logic high level. test d ata-in (tdi) the tdi pin is used to serially input information to the registers and can be connected to the input of any regis- ter. the register between tdi and tdo is chosen by the instruction loaded into the tap instruction register. for information on instruction register loading, see the tap controller state diagram. tdi is internally pulled up and can be disconnected if the tap is unused in an applica - tion. tdi is connected to the most signifcant bit (msb) on any register. 31 30 29 . . . 2 1 0 2 1 0 0 x . . . . . 2 1 0 bypass register instruction register identification register boundary scan register* tap controller selection circuitry selection circuitry tdo tdi tck tms tap controller block diagram
integrated silicon solution, inc. www.issi.com 25 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b test d ata out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending on the cur - rent state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck and tdo is connected to the least signifcant bit (lsb) of any register. performing a tap r eset a reset is performed by forcing tms high (v dd ) for fve rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power-up, the tap is internally reset to ensure that tdo comes up in a high-z state. tap r egisters registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the in - struction register. this register is loaded when it is placed between the tdi and tdo pins. (see tap controller block diagram) at power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as previously described. when the tap controller is in the capture-ir state, the two least signifcant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass reg - ister is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all input and output pins on the sram . several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 confguration has a 75-bit-long register and the x18 confguration also has a 75-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and then placed be - tween the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample-z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identifcation (id) register the id register is loaded with a vendor-specifc, 32-bit code during the capture-dr state when the idcode com - mand is loaded to the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has vendor code and other information described in the identifcation register defnitions table. scan register sizes register bit size bit size name (x18) (x36) instruction 3 3 bypass 1 1 id 32 32 boundary scan 75 75 i dentification register definitions instruction field description 2m x 36 4m x 18 revision number (31:28) reserved for version number. xxxx xxxx device depth (27:23) defnes depth of sram. 2m or 4m 01010 01011 device width (22:18) defnes width of the sram. x36 or x18 00100 00011 issi device id (17:12) reserved for future use. xxxxx xxxxx issi jedec id (11:1) allows unique identifcation of sram vendor. 00001010101 00001010101 id register presence (0) indicate the presence of an id register. 1 1
26 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b tap i nstruction set eight instructions are possible with the three-bit instruction register and all combinations are listed in the instruction code table. three instructions are listed as reserved and should not be used and the other fve instructions are described below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals and cannot preload the input or output buf - fers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/ preload ; instead it performs a capture of the inputs and output ring when these instructions are executed. instruc - tions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the tdi and tdo pins. to execute an instruction once it is shifted in, the tap control - ler must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. because extest is not implemented in the tap controller, this device is not 1149.1 standard compliant. the tap controller recognizes an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is a difference between the instruc - tions, unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specifc, 32- bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample-z the sample-z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded to the instruc - tion register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. it is important to realize that the tap controller clock oper - ates at a frequency up to 10 mhz, while the sram clock runs more than an order of magnitude faster. because of the clock frequency differences, it is possible that during the capture-dr state, an input or output will under-go a transition. the tap may attempt a signal capture while in transition (metastable state). the device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. to guarantee that the boundary scan register will capture the correct signal value, the sram signal must be stabilized long enough to meet the tap controllers capture set-up plus hold times (t cs and t ch ). to insure that the sram clock input is captured correctly, designs need a way to stop (or slow) the clock during a sample/preload instruction. if this is not an issue, it is possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update- dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. b ypass when the bypass instruction is loaded in the instruc - tion register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. r eserved these instructions are not implemented but are reserved for future use. do not use these instructions.
integrated silicon solution, inc. www.issi.com 27 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b instruction codes code instruction description 000 extest captures the input/output ring contents. places the boundary scan register be - tween the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. 001 idcode loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. 010 sample-z captures the input/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. 011 reserved do not use: this instruction is reserved for future use. 100 sample/preload captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. 101 reserved do not use: this instruction is reserved for future use. 110 reserved do not use: this instruction is reserved for future use. 111 bypass places the bypass register between tdi and tdo. this operation does not affect sram operation. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test/idle 11 1 11 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 10 tap controller state diagram
28 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b tap electrical characteristics (v ddq = 1.8v operating range) symbol parameter test conditions min. max. units v oh 1 output high voltage i oh = -1 ma v dd -0.4 v v ol 1 output low voltage i ol = 1 ma 0.5 v v ih input high voltage 1.3 v dd +0.3 v v il input low voltage -0.3 0.7 v i x input load current vss v i v ddq -30 30 ma tap electrical characteristics (v ddq = 3.3v operating range) symbol parameter test conditions min. max. units v oh 1 output high voltage i oh = -4 ma 2.4 v v oh 2 output high voltage i oh = -100 a 2.9 v v ol 1 output low voltage i ol = 8 ma 0.4 v v ol 2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 2.0 v dd +0.3 v v il input low voltage C0.3 0.8 v i x input load current vss v in v ddq C30 30 ma tap electrical characteristics (v ddq = 2.5v operating range) symbol parameter test conditions min. max. units v oh 1 output high voltage i oh = -1 ma 2.0 v v oh 2 output high voltage i oh = -100 a 2.1 v v ol 1 output low voltage i ol = 1 ma 0.4 v v ol 2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage -0.3 0.7 v i x input load current vss v in v ddq C30 30 ma
integrated silicon solution, inc. www.issi.com 29 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b parameter symbol min max units tck cycle time t thth 100 C ns tck high pulse width t thtl 40 C ns tck low pulse width t tlth 40 C ns tms setup t mvth 10 C ns tms hold t thmx 10 C ns tdi setup t dvth 10 C ns tdi hold t thdx 10 C ns tck low to valid data t tlov C 20 ns tap ac electrical characteristics (over o perating range) don't care undefined tck tms tdi tdo t thtl t tl th t thth t mvth t thmx t d vth t thdx 1 2 3 4 5 6 t tlo x t tlo v t ap timing 20 pf tdo gnd 50 vtrig z 0 = 50 tap output load equivalent (1.8v/2.5v/3.3v) input pulse levels 0 to 1.8v/0 to 2.5v/0 to 3.0v input rise and fall times 1.5ns input timing reference levels 0.9v/1.25v/1.5v output reference levels 0.9v/1.25v/1.5v test load termination supply voltage 0.9v/1.25v/1.5v vtrig 0.9v/1.25v/1.5v tap test conditions
30 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b b oundary scan order continued on next page 165 bga 119 bga x36 x18 x36 x18 bit # bump id signal bump id signal bit # bump id signal bump id signal 1 n6 nc n6 nc 1 nc nc 2 n7 nc n7 nc 2 nc nc 3 n10 nc n10 nc 3 nc nc 4 p11 nc p11 nc 4 nc nc 5 p8 a18 p8 a18 5 a18 a18 6 r8 a17 r8 a17 6 a17 a17 7 r9 a16 r9 a16 7 a16 a16 8 p9 a15 p9 a15 8 a15 a15 9 p10 a14 p10 a14 9 a14 a14 10 r10 a13 r10 a13 10 a13 a13 11 r11 a12 r11 a12 11 a12 a12 12 h11 zz h11 zz 12 t7 zz t7 zz 13 n11 dqa0 n11 nc 13 p6 dqa0 p6 nc 14 m11 dqa1 m11 nc 14 n7 dqa1 n7 nc 15 l11 dqa2 l11 nc 15 m6 dqa2 m6 nc 16 k11 dqa6 k11 nc 16 l7 dqa6 l7 nc 17 j11 dqa7 j11 nc 17 k6 dqa7 k6 nc 18 m10 dqa3 m10 dqa8 18 p7 dqa3 p7 dqa8 19 l10 dqa4 l10 dqa7 19 n6 dqa4 n6 dqa7 20 k10 dqa5 k10 dqa6 20 l6 dqa5 l6 dqa6 21 j10 dqa8 j10 dqa5 21 k7 dqa8 k7 dqa5 22 h9 nc h9 nc 22 nc nc 23 h10 nc h10 nc 23 nc nc 24 g11 dqb8 g11 dqa4 24 h6 dqb8 h6 dqa4 25 f11 dqb7 f11 dqa3 25 g7 dqb7 g7 dqa3 26 e11 dqb5 e11 dqa2 26 f6 dqb5 f6 dqa2 27 d11 dqb4 d11 dqa1 27 e7 dqb4 e7 dqa1 28 g10 dqb6 g10 nc 28 h7 dqb6 h7 nc 29 f10 dqb3 f10 nc 29 g6 dqb3 g6 nc 30 e10 dqb2 e10 nc 30 e6 dqb2 e6 nc 31 d10 dqb1 d10 nc 31 d7 dqb1 d7 nc 32 c11 dqb0 c11 dqa0 32 d6 dqb0 d6 dqa0 33 a11 nc a11 a21 33 t1 nc t1 a21 34 b11 nc b11 nc 34 nc nc 35 a10 a11 a10 a11 35 a11 a11 36 b10 a10 b10 a10 36 a10 a10 37 a9 a9 a9 a9 37 g4 a9 g4 a9 38 b9 a8 b9 a8 38 a4 a8 a4 a8 39 c10 nc c10 nc 39 nc nc 40 a8 adv a8 adv 40 b4 adv b4 adv 41 b8 /oe b8 /oe 41 f4 /oe f4 /oe 42 a7 /cke a7 /cke 42 m4 /cke m4 /cke 43 b7 /we b7 /we 43 h4 /we h4 /we 44 b6 clk b6 clk 44 k4 clk k4 clk
integrated silicon solution, inc. www.issi.com 31 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b 165 bga 119 bga x36 x18 x36 x18 bit # bump id signal bump id signal bit # bump id signal bump id signal 45 a6 /ce2 a6 /ce2 45 b6 /ce2 b6 /ce2 46 b5 /bwa b5 /bwa 46 l5 /bwa l5 /bwa 47 a5 /bwb a5 nc 47 g5 /bwb g5 nc 48 a4 /bwc a4 /bwb 48 g3 /bwc g3 /bwb 49 b4 /bwd b4 nc 49 l3 /bwd l3 nc 50 b3 ce2 b3 ce2 50 b2 ce2 b2 ce2 51 a3 /ce1 a3 /ce1 51 e4 /ce1 e4 /ce1 52 a2 a7 a2 a7 52 a7 a7 53 b2 a6 b2 a6 53 a6 a6 54 c2 nc c2 nc 54 nc nc 55 b1 nc b1 nc 55 nc nc 56 a1 nc a1 nc 56 nc nc 57 c1 dqc0 c1 nc 57 d2 dqc0 d2 nc 58 d1 dqc1 d1 nc 58 e1 dqc1 e1 nc 59 e1 dqc2 e1 nc 59 f2 dqc2 f2 nc 60 f1 dqc6 f1 nc 60 g1 dqc6 g1 nc 61 g1 dqc7 g1 nc 61 h2 dqc7 h2 nc 62 d2 dqc3 d2 dqb8 62 d1 dqc3 d1 dqb8 63 e2 dqc4 e2 dqb7 63 e2 dqc4 e2 dqb7 64 f2 dqc5 f2 dqb6 64 g2 dqc5 g2 dqb6 65 g2 dqc8 g2 dqb5 65 h1 dqc8 h1 dqb5 66 h1 nc h1 nc 66 nc nc 67 h2 nc h2 nc 67 nc nc 68 h3 nc h3 nc 68 nc nc 69 j1 dqd8 j1 dqb4 69 k2 dqd8 k2 dqb4 70 k1 dqd7 k1 dqb3 70 l1 dqd7 l1 dqb3 71 l1 dqd5 l1 dqb2 71 m2 dqd5 m2 dqb2 72 m1 dqd4 m1 dqb1 72 n1 dqd4 n1 dqb1 73 j2 dqd6 j2 nc 73 k1 dqd6 k1 nc 74 k2 dqd3 k2 nc 74 l2 dqd3 l2 nc 75 l2 dqd2 l2 nc 75 n2 dqd2 n2 nc 76 m2 dqd1 m2 nc 76 p1 dqd1 p1 nc 77 n1 dqd0 n1 dqb0 77 p2 dqd0 p2 dqb0 78 n2 nc n2 nc 78 nc nc 79 p1 nc p1 nc 79 nc nc 80 r1 mode r1 mode 80 r3 mode r3 mode 81 r2 a4 r2 a4 81 a4 a4 82 p3 a3 p3 a3 82 a3 a3 83 r3 a2 r3 a2 83 a2 a2 84 p2 a5 p2 a5 84 a5 a5 85 r4 a19 r4 a19 85 a19 a19 86 p4 a20 p4 a20 86 t2 a20 t2 a20 87 n5 nc n5 nc 87 nc nc 88 p6 a1 p6 a1 88 n4 a1 n4 a1 89 r6 a0 r6 a0 89 p4 a0 p4 a0 90 * int * int 90 * int * int
32 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b ordering information commercial range: 0c to 70c (vdd = 3.3v / vddq = 2.5v/3.3v) speed x36 x18 package 250mhz IS61NLP204836B-250tq is61nlp409618b-250tq 100 tqfp IS61NLP204836B-250b3 is61nlp409618b-250b3 165 pbga,13x15mm IS61NLP204836B-250m3 is61nlp409618b-250m3 165 pbga,15x17mm IS61NLP204836B-250b2 is61nlp409618b-250b2 119 pbga IS61NLP204836B-250tql is61nlp409618b-250tql 100 tqfp, lead-free IS61NLP204836B-250b3l is61nlp409618b-250b3l 165 pbga,13x15mm, lead-free IS61NLP204836B-250m3l is61nlp409618b-250m3l 165 pbga,15x17mm, lead-free IS61NLP204836B-250b2l is61nlp409618b-250b2l 119 pbga, lead-free 200mhz IS61NLP204836B-200tq is61nlp409618b-200tq 100 tqfp IS61NLP204836B-200b3 is61nlp409618b-200b3 165 pbga,13x15mm IS61NLP204836B-200m3 is61nlp409618b-200m3 165 pbga,15x17mm IS61NLP204836B-200b2 is61nlp409618b-200b2 119 pbga IS61NLP204836B-200tql is61nlp409618b-200tql 100 tqfp, lead-free IS61NLP204836B-200b3l is61nlp409618b-200b3l 165 pbga,13x15mm, lead-free IS61NLP204836B-200m3l is61nlp409618b-200m3l 165 pbga,15x17mm, lead-free IS61NLP204836B-200b2l is61nlp409618b-200b2l 119 pbga, lead-free 166mhz IS61NLP204836B-166tq is61nlp409618b-166tq 100 tqfp IS61NLP204836B-166b3 is61nlp409618b-166b3 165 pbga,13x15mm IS61NLP204836B-166m3 is61nlp409618b-166m3 165 pbga,15x17mm IS61NLP204836B-166b2 is61nlp409618b-166b2 119 pbga IS61NLP204836B-166tql is61nlp409618b-166tql 100 tqfp, lead-free IS61NLP204836B-166b3l is61nlp409618b-166b3l 165 pbga,13x15mm, lead-free IS61NLP204836B-166m3l is61nlp409618b-166m3l 165 pbga,15x17mm, lead-free IS61NLP204836B-166b2l is61nlp409618b-166b2l 119 pbga, lead-free commercial range: 0c to 70c (vdd = 2.5v / vddq = 2.5v) speed x36 x18 package 250mhz is61nvp204836b-250tq is61nvp409618b-250tq 100 tqfp is61nvp204836b-250b3 is61nvp409618b-250b3 165 pbga,13x15mm is61nvp204836b-250m3 is61nvp409618b-250m3 165 pbga,15x17mm is61nvp204836b-250b2 is61nvp409618b-250b2 119 pbga is61nvp204836b-250tql is61nvp409618b-250tql 100 tqfp, lead-free is61nvp204836b-250b3l is61nvp409618b-250b3l 165 pbga,13x15mm, lead-free is61nvp204836b-250m3l is61nvp409618b-250m3l 165 pbga,15x17mm, lead-free is61nvp204836b-250b2l is61nvp409618b-250b2l 119 pbga, lead-free
integrated silicon solution, inc. www.issi.com 33 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b speed x36 x18 package 200mhz is61nvp204836b-200tq is61nvp409618b-200tq 100 tqfp is61nvp204836b-200b3 is61nvp409618b-200b3 165 pbga,13x15mm is61nvp204836b-200m3 is61nvp409618b-200m3 165 pbga,15x17mm is61nvp204836b-200b2 is61nvp409618b-200b2 119 pbga is61nvp204836b-200tql is61nvp409618b-200tql 100 tqfp, lead-free is61nvp204836b-200b3l is61nvp409618b-200b3l 165 pbga,13x15mm, lead-free is61nvp204836b-200m3l is61nvp409618b-200m3l 165 pbga,15x17mm, lead-free is61nvp204836b-200b2l is61nvp409618b-200b2l 119 pbga, lead-free 166mhz is61nvp204836b-166tq is61nvp409618b-166tq 100 tqfp is61nvp204836b-166b3 is61nvp409618b-166b3 165 pbga,13x15mm is61nvp204836b-166m3 is61nvp409618b-166m3 165 pbga,15x17mm is61nvp204836b-166b2 is61nvp409618b-166b2 119 pbga is61nvp204836b-166tql is61nvp409618b-166tql 100 tqfp, lead-free is61nvp204836b-166b3l is61nvp409618b-166b3l 165 pbga,13x15mm, lead-free is61nvp204836b-166m3l is61nvp409618b-166m3l 165 pbga,15x17mm, lead-free is61nvp204836b-166b2l is61nvp409618b-166b2l 119 pbga, lead-free commercial range: 0c to 70c (vdd = 1.8v / vddq = 1.8v) speed x36 x18 package 200mhz please contact issi (sram@issi.com) 166mhz is61nvvp204836b-166tq is61nvvp409618b-166tq 100 tqfp is61nvvp204836b-166b3 is61nvvp409618b-166b3 165 pbga,13x15mm is61nvvp204836b-166m3 is61nvvp409618b-166m3 165 pbga,15x17mm is61nvvp204836b-166b2 is61nvvp409618b-166b2 119 pbga is61nvvp204836b-166tql is61nvvp409618b-166tql 100 tqfp, lead-free is61nvvp204836b-166b3l is61nvvp409618b-166b3l 165 pbga,13x15mm, lead-free is61nvvp204836b-166m3l is61nvvp409618b-166m3l 165 pbga,15x17mm, lead-free is61nvvp204836b-166b2l is61nvvp409618b-166b2l 119 pbga, lead-free
34 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b industrial range: -40c to +85c(vdd = 3.3v / vddq = 2.5v/3.3v) speed x36 x18 package 250mhz IS61NLP204836B-250tqi is61nlp409618b-250tqi 100 tqfp IS61NLP204836B-250b3i is61nlp409618b-250b3i 165 pbga,13x15mm IS61NLP204836B-250m3i is61nlp409618b-250m3i 165 pbga,15x17mm IS61NLP204836B-250b2i is61nlp409618b-250b2i 119 pbga IS61NLP204836B-250tqli is61nlp409618b-250tqli 100 tqfp, lead-free IS61NLP204836B-250b3li is61nlp409618b-250b3li 165 pbga,13x15mm, lead-free IS61NLP204836B-250m3li is61nlp409618b-250m3li 165 pbga,15x17mm, lead-free IS61NLP204836B-250b2li is61nlp409618b-250b2li 119 pbga, lead-free 200mhz IS61NLP204836B-200tqi is61nlp409618b-200tqi 100 tqfp IS61NLP204836B-200b3i is61nlp409618b-200b3i 165 pbga,13x15mm IS61NLP204836B-200m3i is61nlp409618b-200m3i 165 pbga,15x17mm IS61NLP204836B-200b2i is61nlp409618b-200b2i 119 pbga IS61NLP204836B-200tqli is61nlp409618b-200tqli 100 tqfp, lead-free IS61NLP204836B-200b3li is61nlp409618b-200b3li 165 pbga,13x15mm, lead-free IS61NLP204836B-200m3li is61nlp409618b-200m3li 165 pbga,15x17mm, lead-free IS61NLP204836B-200b2li is61nlp409618b-200b2li 119 pbga, lead-free 166mhz IS61NLP204836B-166tqi is61nlp409618b-166tqi 100 tqfp IS61NLP204836B-166b3i is61nlp409618b-166b3i 165 pbga,13x15mm IS61NLP204836B-166m3i is61nlp409618b-166m3i 165 pbga,15x17mm IS61NLP204836B-166b2i is61nlp409618b-166b2i 119 pbga IS61NLP204836B-166tqli is61nlp409618b-166tqli 100 tqfp, lead-free IS61NLP204836B-166b3li is61nlp409618b-166b3li 165 pbga,13x15mm, lead-free IS61NLP204836B-166m3li is61nlp409618b-166m3li 165 pbga,15x17mm, lead-free IS61NLP204836B-166b2li is61nlp409618b-166b2li 119 pbga, lead-free industrial range: -40c to +85c(vdd = 2.5v / vddq = 2.5v) speed x36 x18 package 250mhz is61nvp204836b-250tqi is61nvp409618b-250tqi 100 tqfp is61nvp204836b-250b3i is61nvp409618b-250b3i 165 pbga,13x15mm is61nvp204836b-250m3i is61nvp409618b-250m3i 165 pbga,15x17mm is61nvp204836b-250b2i is61nvp409618b-250b2i 119 pbga is61nvp204836b-250tqli is61nvp409618b-250tqli 100 tqfp, lead-free is61nvp204836b-250b3li is61nvp409618b-250b3li 165 pbga,13x15mm, lead-free is61nvp204836b-250m3li is61nvp409618b-250m3li 165 pbga,15x17mm, lead-free is61nvp204836b-250b2li is61nvp409618b-250b2li 119 pbga, lead-free
integrated silicon solution, inc. www.issi.com 35 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b speed x36 x18 package 200mhz is61nvp204836b-200tqi is61nvp409618b-200tqi 100 tqfp is61nvp204836b-200b3i is61nvp409618b-200b3i 165 pbga,13x15mm is61nvp204836b-200m3i is61nvp409618b-200m3i 165 pbga,15x17mm is61nvp204836b-200b2i is61nvp409618b-200b2i 119 pbga is61nvp204836b-200tqli is61nvp409618b-200tqli 100 tqfp, lead-free is61nvp204836b-200b3li is61nvp409618b-200b3li 165 pbga,13x15mm, lead-free is61nvp204836b-200m3li is61nvp409618b-200m3li 165 pbga,15x17mm, lead-free is61nvp204836b-200b2li is61nvp409618b-200b2li 119 pbga, lead-free 166mhz is61nvp204836b-166tqi is61nvp409618b-166tqi 100 tqfp is61nvp204836b-166b3i is61nvp409618b-166b3i 165 pbga,13x15mm is61nvp204836b-166m3i is61nvp409618b-166m3i 165 pbga,15x17mm is61nvp204836b-166b2i is61nvp409618b-166b2i 119 pbga is61nvp204836b-166tqli is61nvp409618b-166tqli 100 tqfp, lead-free is61nvp204836b-166b3li is61nvp409618b-166b3li 165 pbga,13x15mm, lead-free is61nvp204836b-166m3li is61nvp409618b-166m3li 165 pbga,15x17mm, lead-free is61nvp204836b-166b2li is61nvp409618b-166b2li 119 pbga, lead-free industrial range: -40c to +85c(vdd = 1.8v / vddq = 1.8v) speed x36 x18 package 200mhz please contact issi (sram@issi.com) 166mhz is61nvvp204836b-166tqi is61nvvp409618b-166tqi 100 tqfp is61nvvp204836b-166b3i is61nvvp409618b-166b3i 165 pbga,13x15mm is61nvvp204836b-166m3i is61nvvp409618b-166m3i 165 pbga,15x17mm is61nvvp204836b-166b2i is61nvvp409618b-166b2i 119 pbga is61nvvp204836b-166tqli is61nvvp409618b-166tqli 100 tqfp, lead-free is61nvvp204836b-166b3li is61nvvp409618b-166b3li 165 pbga,13x15mm, lead-free is61nvvp204836b-166m3li is61nvvp409618b-166m3li 165 pbga,15x17mm, lead-free is61nvvp204836b-166b2li is61nvvp409618b-166b2li 119 pbga, lead-free automotive(a3) range: -40c to +125c(vdd = 3.3v / vddq = 2.5v/3.3v) speed x36 x18 package please contact issi (sram@issi.com) automotive(a3) range: -40c to +125c(vdd = 2.5v / vddq = 2.5v) speed x36 x18 package please contact issi (sram@issi.com) automotive(a3) range: -40c to +125c(vdd = 1.8v / vddq = 1.8v) speed x36 x18 package please contact issi (sram@issi.com)
36 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b
integrated silicon solution, inc. www.issi.com 37 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b
38 integrated silicon solution, inc. www.issi.com rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b 1. controlling dimension : mm . note : package outline 08/28/2008
integrated silicon solution, inc. www.issi.com 39 rev. a 8/4/2014 IS61NLP204836B/is61nvp/nvvp204836b is61nlp409618b/is61nvp/nvvp409618b note : 1. controlling dimension : mm package outline 12/10/2007

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